The present invention relates in particular to the CMOS Static Random Access Memory (RAM) art. Specifically, a Static RAM cell is disclosed having a reduced transistor count and a corresponding reduced surface area.
A standard CMOS Static RAM cell typically consists of six field effect transistors (FETs), as shown more particularly in FIG. 1. The RAM cell stores data as a voltage differential on first and second nodes 11 and 12 of a cross-coupled latch circuit. The cross-coupled latch circuit includes PMOS pull-up transistors 14 and 15 serially connected with two pulldown NMOS transistors 17 and 18. The state of the latch is changed by forcing the nodes 11 and 12 to a voltage differential representing a desired state identified by the data on complementary bit lines B0 and B1. During a write operation the Word line is enabled, thus connecting complementary bit lines B0 and B1 through access transistors 20 and 21 to the nodes 11 and 12. The latch circuit regeneratively forces the nodes 11 and 12 to assume the states of bit lines B0 and B1.
The conventional SRAM of FIG. 1 is constructed so that during a read operation, the loading presented by bit lines B0, B1 does not disturb the state of the cross-coupled latch, while at the same time during a write operation, sufficient current is supplied to nodes 11 and 12 from bit lines B0, B1 to force the latch to change state.
These competing objectives are accomplished by selectively choosing the current carrying capacity of the latch transistors 14-18, and the access transistors 20 and 21. The selection of the current carrying capacity of these devices leads to the use of devices which are larger than otherwise needed to store the data. The larger devices, in turn, expand the substrate area occupied by each CMOS RAM cell.
The present invention is designed to reduce the size of the CMOS RAM cell in more than one way. The reduction in surface area for each CMOS RAM cell provides a desirable increase in memory density, and permits larger memories to be implemented on the same surface area of the substrate.